In the Proceedings of the 5th European Congress on Intelligent Techniques and Soft Computing, vol. III, pp. 2495-2499, Aachen, Germany, September 8-11, 1998.

Abstract

A hardware architecture of the Self-Organizing Map (SOM) has been developed. The architecture is fully based on a pipelined structure, which makes it suitable for real-time data processing. The architecture has been implemented using Very High Speed Integrated Circuit Hardware Description Language (VHDL) and Synopsys's logic synthesis tool. The VHDL code was synthesized to Xilinx XC4000-series FPGA library. The simulated speed of the synthesized design was 20 MHz when routing delay was not considered.